Embedded Systems

Design and implementation of a bit-serial accelerator architecture based on UltraTrail

In­tern­ship

Ab­stract

Ul­tra­Trail is a low-power hard­ware ac­cel­er­a­tor for deep neural net­works (DNN) de­vel­oped at our chair. To re­duce mem­ory over­head and com­pu­ta­tional cost, both DNN pa­ra­me­ters and input fea­tures are quan­tized to fixed-point num­bers with small bitwidth (e.g. 8 bit). While it is pos­si­ble to freely change the used datatype dur­ing de­sign time, once the chip is man­u­fac­tured, it will stay fixed. One ap­proach of main­tain­ing flex­i­bil­ity even in the final chip is to use bit-se­r­ial com­pu­ta­tion. Here, the operands are processed bit by bit, in­stead of a sin­gle op­er­a­tion.

The goal of this work is to ex­tend or re­design the cur­rent Ul­tra­Trail im­ple­men­ta­tion with a bit-se­r­ial dataflow and to ex­plore the ben­e­fits or draw­backs of such a de­sign.

Re­quire­ments

  • Suc­cess­fully at­teded the lec­ture “En­twurf und Syn­these Ein­bet­teteter Sys­teme” or knowl­edge in hard­ware de­sign using Sys­temVer­ilog or VHDL
  • Basic knowl­edge in deep neural net­works (op­tional)
  • Python (op­tional)

Con­tact

Palom­ero Bernardo, Paul

Bring­mann, Oliver